Data Converters

An important focus area of Chain-IC is analog-to-digital and digital-to-analog conversion. ADC’s and DAC’s are usually at the heart of a mixed-signal integrated circuit. A data converter needs to be designed well in order to meet the often stringent system specifications. A wide variety of ADC and DAC topologies exist, all having their advantages and challenges that require a careful tradeoff to come to a solution that is optimal for the application. In some cases also hybrid solutions can be interesting to consider, where one can benefit from the strong points of different topologies. Together with our customer we can explore the options and select the most promising architecture.

Below some standard ADC architectures are given.

Flash ADC

A flash ADC uses 2^N-1 comparators to achieve an N bit resolution. A decoder is used to generate a binary output based on the comparator decisions. The flash converter can achieve a high conversion rate due to the large amount of parallel decisions. This comes however at the cost of a relatively large power and area usage. Furthermore, the accuracy is limited to approximately 8 bits without calibration, due to component mismatch.

Pipeline ADC

In a pipeline ADC the conversion process is sub-divided into multiple stages, each having one to a few bits. The output of each stage is fed into digital correction logic. Due to the sub-ranging principle there is no exponential hardware and power increase when increasing the number of bits, as is the case with the flash converter. Furthermore a better accuracy can be achieved compared to the flash converter because of the linearity improvement as a result of the lower resolution of each stage.


A Successive Approximation Register (SAR) ADC samples the input signal on a capacitor array, and compares the signal to different levels set by a DAC. After each applied level a comparison is performed, and based on the output the SAR logic determines the next reference level. In this way N cycles are required to obtain an N-bit signal. Due to the limited amount of hardware that is required, good power and area specifications can be achieved. The main disadvantage of a SAR converter is its limited speed because of the fact that N conversion cycles are required. Furthermore the accuracy is limited due to capacitor mismatch and comparator offset.

Sigma-Delta ADC

The three ADC topologies discussed above all fall in the category of the Nyquist converters. These topologies can convert wideband signals from the analog to the digital domain. However, when a high-resolution output is required while the bandwidth of the signal is limited, a different class of converters can be interesting to use, which is based on the sigma-delta modulation principle. This type of converter has a relatively low resolution quantizer, but instead uses a high sample rate to get an accurate representation of the input signal. The quantization noise that is inherent to the system is shaped to higher frequencies. These noise shaping characteristics are determined by the order of the loop filter and the oversample rate.